Field of the Invention
The present invention relates to a high-voltage diode having a well-type zone of a first conductivity type, which is provided in a first main surface of a semiconductor body having a second conductivity type, being opposite to the first conductivity type. A metal contact is provided on the well-type zone. A rear side metallization is located, opposite to the metal contact, on a second main surface of the semiconductor body. The second main surface is located opposite to the first main surface and an edge termination with a channel stopper is provided. A passivation layer, which is provided on the first main surface in a region between the metal contact and the channel stopper, covers a pn junction issuing at the first main surface.
To date, high-voltage diodes, which are provided for relatively high voltages of, in particular, above about 400 V, have been provided, and use planar structures, with edge terminations containing field plates, field rings, dielectric insulating layers, semi-insulating coverings and a varying doping in the edge region. In this case, these measures are employed individually or in combination, it perfectly well being the case that, by way of example, field plates, field rings and dielectric insulating layers are also used jointly.
In this case, it has been shown that, during the fabrication of the diode, even more steps are necessary for an edge termination that satisfies the requirements made of it than for setting the desired on-state and switching properties. Thus, by way of example, diode edges based on field plates require relatively complicated fabrication processes.
Specifically, in the reference by C. Mingues and G. Charitat, titled xe2x80x9cEfficiency of Junction Termination Techniques vs. Oxide Trapped Chargesxe2x80x9d, 1997 IEEE International Symposium on Power Semiconductor Devices and ICs, Weimar, pages 137 to 140, edge terminations with field rings, semi-insulating layers or a junction termination extension (JTE) are compared with one another especially with regard to their sensitivity to oxide charges. In this case, the use of SIPOS techniques is recommended as semi-insulating layers for high-voltage applications.
European Patent EP 0 341 453 B1, corresponding to U.S. Pat. No. 4,954,868, discloses a MOS semiconductor component for a high reverse voltage, in which field plates are disposed on insulating layers of different thicknesses. In this case, some of the field plates serve as channel stoppers. In diodes, such field plates used as channel stoppers are often connected to the rear side potential of the diode by a p-conducting region in the edge region, even though a connection via an n-conducting region would inherently be more advantageous because a p-conducting channel could thereby be reliably prevented. However, given an otherwise customary fabrication process, an additional mask step would be necessary for such a connection via an n-conducting region.
When sawing a wafer into individual chips, so-called chipping stoppers are intended to prevent crystal defects from propagating from the sawing edge into the active region of the respective chips. The chipping stoppers are usually realized by a field oxide between the functional edge region of the chip and the sawing line.
If pn junctions having a high blocking capability are only covered with dielectric passivation layers, then under the action of external charges which are attributable for example to moisture, alkaline or metallic contamination, etc., changes in the long-term blocking stability can be observed in the event of blocking loading of the pn junction. These changes are brought about by a drift of ionic charges in the electric field of the reverse-biased pn junction on or in the passivation layer. Depending on the sign of the ionic charges and also depending on the structure of the edge termination, that is to say depending on the so-called edge contour, the ionic charges can lead to an increase or to a decrease in the blocking capability of the pn junction. In the case of a diode with a p-conducting anode, in this case, as the doping in the n-conducting base decreases and therefore as the bulk blocking capability of the diode increases, as a result of a greater induction effect, the influence of such surface charges in and on the passivation layer increases, which leads to a dramatic increase in the risk of blocking instabilities. In this connection, reference should be made to the so-called Yoshida effect; when using insulator layers for passivation, a drift in the reverse voltage is occasionally observed on account of an injection of hot electrons during the on-state loading when changing over to the blocking state of the pn junction.
By using semi-insulating layers directly on the pn junctions, the influence of such surface charges can be suppressed given suitable settings of the layer and interface parameters, such as, for example, of the layer thickness and doping of the semi-insulating layers. The semi-insulating layers which are currently used for the passivation of pn junctions contain, for example, amorphous silicon (a-Si) or hydrogen-doped amorphous carbon (a-C:H), as are described in European Patents EP 0 400 178 B1 and EP 0 381 111 B1 (corresponding to U.S. Pat. No. 5,039,358). With these semi-insulating layers, parasitic effects, such as an elevated reverse current or the formation of inversion layers, can be avoided given corresponding optimization of the amorphous-crystalline heterojunctions between the layers and the electrically active silicon substrate. Moreover, semi-insulating passivation layers can actively build up image charges by virtue of their finite state density and thus shield extraneous charges that penetrate externally, and also dissipate injected charge carriers by virtue of their finite specific conductivity. Overall, a semi-insulating passivation thus leads to a significantly improved long-term stability compared with a dielectric passivation.
It is accordingly an object of the invention to provide a high-voltage diode and a method for fabricating the high-voltage diode that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has a rating for reverse voltages of, in particular, above about 400 V and preferably above about 500 V, and can be fabricated with the least possible process complexity and thus a small number of photo technologies and, in the edge region, can readily be equipped with a channel stopper for avoiding leakage currents and a chipping stopper for limiting the extent of saving defects; moreover, the intention is to provide a method for fabricating such a high-voltage diode.
With the foregoing and other objects in view there is provided, in accordance with the invention, a high-voltage diode. The diode contains a semiconductor body having a first main surface and a second main surface disposed opposite the first main surface, the semiconductor body is formed of a second conductivity type being opposite to a first conductivity type. A well-type zone of the first conductivity type is disposed in the first main surface of the semiconductor body. A metal contact is disposed on the well-type zone. A rear side metallization is disposed on the second main surface of the semiconductor body and disposed opposite to the metal contact. An edge termination having a channel stopper is provided. A passivation layer is disposed on the first main surface in a region between the metal contact and the channel stopper. The passivation layer covers a pn junction issuing at the first main surface. The passivation layer contains an amorphous carbon doped with hydrogen or an amorphous silicon and serves as a chipping stopper in a region of the semiconductor body outside the channel stopper. At least one edge is provided as an alignment structure disposed in the first main surface in a region of the well-type zone.
The measures of producing the masking insulating layer on the semiconductor body and the patterning of the mask insulating layer for the purpose of producing at least one window for the well-type zone each serve individually per se to enable a high-voltage diode which can be fabricated with a low outlay for masks and alignment and has a channel stopper, chipping stopper, etc. These measures can advantageously be employed jointly. It goes without saying, however, that it is also possible to provide a high-voltage diode that realizes only one of these measures.
The high-voltage diode according to the invention may be a fast diode exhibiting switching strength or, alternatively, a rectifier and universal diode in various voltage and current classes. The high-voltage diode may have one or a plurality of field rings depending on the desired voltage class in its edge region.
Preferably, in the case of the high-voltage diode according to the invention, the semiconductor body contains n-conducting silicon into which a p-conducting well-type zone is introduced.
Instead of an n-conducting silicon body, however, it is also possible to provide a p-conducting silicon body having an n-conducting well-type zone.
The semiconductor material is not limited to silicon. Instead of silicon, it is also possible to use, by way of example, SiC or an AIIIBv semiconductor material.
In accordance with an added feature of the invention, the edge termination has at least one field ring.
In accordance with an additional feature of the invention, the channel stopper is provided on the semiconductor body. More specifically, the channel stopper is preferably provided on a region of the first conductivity type.
In accordance with a further feature of the invention, a field stop layer of the second conductivity type is disposed between the semiconductor body and the rear side metallization. A doped emitter layer of the second conductivity type is disposed between the semiconductor body and the rear side metallization being a cathode metallization.
In accordance with another feature of the invention, the alignment structure is one of a plurality of alignment structures, the alignment structures contain silicon steps in the first main surface with a height of between about 10-1,000 nm, preferably with a height of between about 50-200 nm.
In accordance with another additional feature of the invention, the alignment structures are located outside the metal contact being an anode contact.
In accordance with another further feature of the invention, the semiconductor body has a sawing edge, and the passivation layer does not reach as far as the sawing edge.
In accordance with a further added feature of the invention, an annular zone of the first conductivity type, being uncovered at the first main surface, is disposed in a region of the sawing edge.
In accordance with a further additional feature of the invention, the well-type zone is doped with a dose of 1.3-3xc3x971012 dopant atoms cmxe2x88x922 to operate the high-voltage diode as a fast freewheeling diode. The well-type zone has a surface region doped with a dose of between 1.3xc3x971012 dopant atoms cmxe2x88x922 and 5xc3x971013 dopant atoms cmxe2x88x922.
In accordance with a concomitant feature of the invention, the edge termination has a plurality of field rings.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a high-voltage diode. The method includes the steps of:
(a) producing a mask insulating layer on a semiconductor body;
(b) patterning the mask insulating layer resulting in a patterned mask insulation layer and windows, at least one of the windows provided for a well-type zone;
(c) producing steps functioning as alignment structures in the semiconductor body through the windows;
(d) producing the well-type zone through the window with in each case a first conductivity type opposite to a second conductivity type of the semiconductor body;
(e) removing the patterned mask insulating layer;
(f) applying and patterning a passivation layer using a lithography step aligned using the alignment structures resulting in a patterned passivation layer with further windows, the passivation layer is made from amorphous carbon doped with hydrogen or amorphous silicon;
(g) applying and patterning a metal contact and a channel stopper in the further windows of the patterned passivation layer on a front side of the well-type zone and of the semiconductor body respectively; and
(h) applying a metallization on a rear side of the semiconductor body.
In accordance with an added mode of the invention, there is the step of patterning the mask insulating layer for use in forming a field ring and a chipping stopper ring during method step (b).
In accordance with an additional mode of the invention, at least one of the following steps is performed before or after method step (d):
(i) thinning by grinding and/or etching of the semiconductor body to a final thickness;
(j) introducing a doping of the second conductivity type for forming a field stop layer on the rear side of the semiconductor body and outdiffusing the doping;
(k) introducing an n-conducting doping on the rear side of the semiconductor body as a rear side emitter using ion implantation;
(l) introducing heavy metal atoms for setting a charge carrier lifetime; and
(m) diffusing the heavy metal atoms.
In accordance with another mode of the invention, there is the step of performing one of the method steps (l) and (m) before or after method step (d).
In accordance with a further mode of the invention, there is the step of carrying out the method steps (i) to (k) after method steps (l) and (m) are completed.
In accordance with a further added mode of the invention, there is the step of carrying out the following method step after method step (e) and before method step (f):
(n) irradiating at least one of the semiconductor body and the well-type zone and rings contained therein for setting the charge carrier lifetime.
In accordance with a further additional mode of the invention, the following method step is carried out after method step (f) and before method step (g):
(o) irradiating at least one of the semiconductor body and the well-type zone and rings contained therein for setting the charge carrier lifetime.
In accordance with another added mode of the invention, at least one of the following method steps is carried out after method step (g):
(p) heat treating a front side metallization made of the metal contact and the channel stopper; and
(q) irradiating the semiconductor body and the zone and rings contained therein for setting the charge carrier lifetime.
In accordance with another additional mode of the invention, there is the step of carrying out method steps (i) and (k) after method step (q).
In accordance with another further mode of the invention, there is the step of carrying out the following method step after method step (h):
(r) heat treating the metallization on the rear side of the semiconductor body.
In accordance with an added mode of the invention, there is the step of forming the mask insulating layer in a furnace process with moist oxidation up to a layer thickness of about 0.5 xcexcm.
In accordance with an additional mode of the invention, there is the step of introducing the alignment structures into the semiconductor body by etching down to a depth between 10-1,000 nm, preferably to a depth between 50-200 nm. Preferably, an isotropic etching is used for the etching.
In accordance with a further mode of the invention, there is the step of providing the alignment structures with a spacing with respect to the windows.
In accordance with a concomitant feature of the invention, there is the step of carrying out only three phototechnology steps for fabricating the high-voltage diode.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a high-voltage diode and a method for fabricating the high-voltage diode, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.